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Job Description :
In your new role, you will:

  • Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip
  • Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures
  • Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification
  • Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at/TDF/Bridging/Cell-aware/iddq fault models
  • Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations.
  • Hands on experience in analysis and debug of above-mentioned test domains
  • Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out

Your ProfileYou are best equipped for this task if you have:

  • B.Tech or M.Tech relevant work experience and specialization in VLSI design
  • Strong hands-on technical experience in DFT implementation and verification of Clusters & SoCs
  • Experience in low-power and equivalence checks will be a plus
  • Expert user of industry standard tools for DFT signoff
  • Experience in scripting languages (shell, perl, tcl) and Make flow
  • Must be well organized, methodical and detail oriented

Benefits
What we offer you at Bangalore
In India a team of 200 people works on hardware and software development for automotive and chip card & security solutions.



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